使用HDL代码检查器来支持IP入口检查——一个需求分析

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI:10.1109/DSD.2002.1115393

Ronny Frevert, Steffen Rülke, Torsten Schäfer, F. Dresig

{"title":"使用HDL代码检查器来支持IP入口检查——一个需求分析","authors":"Ronny Frevert, Steffen Rülke, Torsten Schäfer, F. Dresig","doi":"10.1109/DSD.2002.1115393","DOIUrl":null,"url":null,"abstract":"Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed evaluation table will help to evaluate and select HDL code checkers for particular requirements.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"118 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Use of HDL code checkers to support the IP entrance check - a requirement analysis\",\"authors\":\"Ronny Frevert, Steffen Rülke, Torsten Schäfer, F. Dresig\",\"doi\":\"10.1109/DSD.2002.1115393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed evaluation table will help to evaluate and select HDL code checkers for particular requirements.\",\"PeriodicalId\":330609,\"journal\":{\"name\":\"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools\",\"volume\":\"118 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSD.2002.1115393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2002.1115393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

用于编码风格分析的系统，即所谓的硬件描述语言(HDL)代码检查器，可以完成IP入口检查的重要贡献，即系统设计中可重用组件的选择、符合性测试和质量评估。本文从一个具体的工业环境中总结了对HDL代码检查器的相关要求。建议的评估表将有助于评估和选择特定要求的HDL代码检查器。

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Use of HDL code checkers to support the IP entrance check - a requirement analysis

Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed evaluation table will help to evaluate and select HDL code checkers for particular requirements.

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Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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