C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus
{"title":"在200mm GeOI晶圆上用Si工艺线制备高k和金属栅极的0.12μm p - mosfet","authors":"C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus","doi":"10.1109/ESSDERC.2007.4430977","DOIUrl":null,"url":null,"abstract":"Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers\",\"authors\":\"C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus\",\"doi\":\"10.1109/ESSDERC.2007.4430977\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430977\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430977","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers
Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
