N. Zhan, K. L. Ng, M. Poon, C. Kok, M. Chan, H. Wong
{"title":"高品质氧化铪栅极电介质的特性","authors":"N. Zhan, K. L. Ng, M. Poon, C. Kok, M. Chan, H. Wong","doi":"10.1109/HKEDM.2002.1029153","DOIUrl":null,"url":null,"abstract":"Hafnium oxide (HfO/sub 2/) was investigated as an alternative possible gate dielectric. A MOS capacitor using HfO/sub 2/ as dielectric was fabricated and studied. The HfO/sub 2/ film was formed by direct sputtering of Hf in O/sub 2/ and Ar ambient on to a Si substrate and post-sputtering rapid thermal annealing (RTA). XPS results showed that the interface layer formed between the HfO/sub 2/ and the Si substrate was affected by the RTA time within the 500/spl deg/C to 600/spl deg/C annealing temperature. The interface layer was mainly composed of hafnium silicate and had high interface trap density. Increase in RTA time was found to lower the effective barrier height of the layer and the FN tunneling current.","PeriodicalId":154545,"journal":{"name":"Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Characteristics of high quality hafnium oxide gate dielectric\",\"authors\":\"N. Zhan, K. L. Ng, M. Poon, C. Kok, M. Chan, H. Wong\",\"doi\":\"10.1109/HKEDM.2002.1029153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Hafnium oxide (HfO/sub 2/) was investigated as an alternative possible gate dielectric. A MOS capacitor using HfO/sub 2/ as dielectric was fabricated and studied. The HfO/sub 2/ film was formed by direct sputtering of Hf in O/sub 2/ and Ar ambient on to a Si substrate and post-sputtering rapid thermal annealing (RTA). XPS results showed that the interface layer formed between the HfO/sub 2/ and the Si substrate was affected by the RTA time within the 500/spl deg/C to 600/spl deg/C annealing temperature. The interface layer was mainly composed of hafnium silicate and had high interface trap density. Increase in RTA time was found to lower the effective barrier height of the layer and the FN tunneling current.\",\"PeriodicalId\":154545,\"journal\":{\"name\":\"Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HKEDM.2002.1029153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HKEDM.2002.1029153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characteristics of high quality hafnium oxide gate dielectric
Hafnium oxide (HfO/sub 2/) was investigated as an alternative possible gate dielectric. A MOS capacitor using HfO/sub 2/ as dielectric was fabricated and studied. The HfO/sub 2/ film was formed by direct sputtering of Hf in O/sub 2/ and Ar ambient on to a Si substrate and post-sputtering rapid thermal annealing (RTA). XPS results showed that the interface layer formed between the HfO/sub 2/ and the Si substrate was affected by the RTA time within the 500/spl deg/C to 600/spl deg/C annealing temperature. The interface layer was mainly composed of hafnium silicate and had high interface trap density. Increase in RTA time was found to lower the effective barrier height of the layer and the FN tunneling current.