Design and FPGA Implementation of a Programmable Data Rate PSK Digital Demodulator for Onboard and Ground Applications

In this paper, the design and FPGA implementation of a Digital QPSK Demodulator which supports variable data rates varying from 4.88Kbps to 2Mbps and higher is described. The paper presents the design of carrier and symbol recovery loops in details. The design is made platform independent so that it can be ported to any FPGA device. Proposed design is targeted for Xilinx Virtex-II pro FPGA xc2vp50-6ff 1152 for Hardware proof of concept. The complete demodulator occupies only 13% of the available logic slices in Xilinx Virtex-II pro FPGA device.