批量CMOS 20MS/s 7b闪存ADC

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156643

Y. Fujita, E. Masuda, S. Sakamoto, T. Sakaue, Y. Sato

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引用次数: 3

摘要

本文将介绍一种3.5μm体CMOS si栅极工艺，该工艺应用于单5V电源供电的20MS/s闪存A/D转换器的设计。通过在比较器阵列中使用非采样放大器，以150mW的功耗实现了7b的精度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A bulk CMOS 20MS/s 7b flash ADC

A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.

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来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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