微处理器/加速器共生中的实时原型设计

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) Pub Date : 1998-06-03 DOI:10.1109/IWRSP.1998.676665

J. Becker, R. Hartenstein

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引用次数: 3

摘要

本文介绍了一种新的粗粒度动态可重构硬件平台，并给出了一种基于实时约束的协同主机/加速器平台原型设计通用模型。在此基础上，提出了一种新的并行化编译方法，并将“垂直”并行化技术应用于这种结构可编程加速器。为了进行实时约束分析和实现，解释了主机/加速器执行的任务性能估计过程。此外，本文还解释了多任务应用程序的总体执行时间估计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Real-time prototyping in microprocessor/accelerator symbiosis

The paper introduces a new coarse-grained dynamically reconfigurable hardware platform and a general model for prototyping cooperating host/accelerator platforms under real-time constraints. A new parallelizing compilation method derived from this model is explained, whereas novel "vertical" parallelization techniques are applied for such structural programmable accelerators. For performing real-time constraint analysis and fulfilment the process of task performance estimation for host/accelerator executions is explained. Additionally the paper explained the overall execution time estimation of multi-task applications.

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来源期刊

Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)

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