{"title":"建模互连为未来的VLSI电路应用","authors":"Manodipan Sahoo","doi":"10.1049/pbcs073g_ch7","DOIUrl":null,"url":null,"abstract":"This chapter discusses the various methods of electrical modelling of CNT- and GNR-based nano-interconnects. It also presents the ABCD parameter matrix-based method for the modelling of performance and signal integrity effects in CNT- and GNR-based VLSI nano-interconnects. The developed methodology is proven to be almost 100% accurate as SPICE with huge reduction in the computational burden. It is pointed out that both CNTs and GNRs have tremendous potential in becoming the next generation VLSI interconnects.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"265 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Modelling interconnects for future VLSI circuit applications\",\"authors\":\"Manodipan Sahoo\",\"doi\":\"10.1049/pbcs073g_ch7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This chapter discusses the various methods of electrical modelling of CNT- and GNR-based nano-interconnects. It also presents the ABCD parameter matrix-based method for the modelling of performance and signal integrity effects in CNT- and GNR-based VLSI nano-interconnects. The developed methodology is proven to be almost 100% accurate as SPICE with huge reduction in the computational burden. It is pointed out that both CNTs and GNRs have tremendous potential in becoming the next generation VLSI interconnects.\",\"PeriodicalId\":417544,\"journal\":{\"name\":\"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects\",\"volume\":\"265 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/pbcs073g_ch7\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/pbcs073g_ch7","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modelling interconnects for future VLSI circuit applications
This chapter discusses the various methods of electrical modelling of CNT- and GNR-based nano-interconnects. It also presents the ABCD parameter matrix-based method for the modelling of performance and signal integrity effects in CNT- and GNR-based VLSI nano-interconnects. The developed methodology is proven to be almost 100% accurate as SPICE with huge reduction in the computational burden. It is pointed out that both CNTs and GNRs have tremendous potential in becoming the next generation VLSI interconnects.
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