A fault model for switch-level simulation of gate-to-drain shorts

An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.