采用0.18 CMOS技术的20:1复用器的3.2 Gbit/s CML发射机

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706563

C. Hsiao, M. Kao, C. Jen, Y. Hsu, P. Yang, C. Chiu, J. Wu, S. Hsu, Y. Hsu

{"title":"采用0.18 CMOS技术的20:1复用器的3.2 Gbit/s CML发射机","authors":"C. Hsiao, M. Kao, C. Jen, Y. Hsu, P. Yang, C. Chiu, J. Wu, S. Hsu, Y. Hsu","doi":"10.1109/MIXDES.2006.1706563","DOIUrl":null,"url":null,"abstract":"In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology\",\"authors\":\"C. Hsiao, M. Kao, C. Jen, Y. Hsu, P. Yang, C. Chiu, J. Wu, S. Hsu, Y. Hsu\",\"doi\":\"10.1109/MIXDES.2006.1706563\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706563\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706563","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

为了在高速网络应用中与8/10B编码器集成，研制了一种采用20:1复用器的3.2Gb/s CML发射机。与常见的10:1多路复用器相比，这种20:1的发射机将路由器或交换机所需的工作频率降低了一半。采用基于双相源耦合逻辑的差分电路实现了20:1的串行化，降低了噪声影响。嵌入了一个低功耗锁相环，用于在片上产生双相时钟。宽带低功率高速CML输出缓冲器可提供高达10Gb/s的250mV输出电压摆幅。整体芯片尺寸为650mumtimes950mum，功耗为104 mW，速度为3.2Gb/s

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A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology

In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s

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Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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