基于栅极工程的超结垂直IGBT电容性分析

Namrata Gupta, Alok Naugarhiya
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引用次数: 0

摘要

提出了一种栅极功函数随台阶氧化层厚度变化的1.4 kv级超结垂直IGBT (DMG-SJIGBT)。两种不同的工作功能材料,P+和N+多晶硅被用作栅极多晶硅,氧化物的厚度在x方向上变化。所有的阶梯式氧化物通过顶部的金属连接。该结构的栅极氧化物在发射极处较窄,在集电极处较宽,以提高器件性能。结果发现,DMG-SJIGBT的导通电阻(ron - a)由于这种结构修饰而降低了23%。栅极工程通过增大栅极-发射极电容(CGE)和减小栅极-集电极电容(CGC)来提高导通率,从而降低开关延迟。为了提高性能指标,对栅极长度进行了优化。使用SILVACO的混合模式模块进行电容电压分析。此外,还测量了栅极电荷和FOM,表明所提出的器件分别降低了36%和34%,表明性能增强。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Capacitive Analysis of Superjunction Vertical IGBT with Gate Engineering
This paper proposed a 1.4kV-class superjunction vertical IGBT (DMG-SJIGBT) with gate workfunction variation along with stepped oxide thickness. Two distinct workfunction materials, P+ and N+ polysilicon are used as gate poly and oxide thickness is varied in x-direction. All the stepped oxide is connected via metal on the top. The proposed structure's gate oxide is narrow at the emitter and wide at the collector to improve the device performance. It has been discovered that the ON-resistance (Ron.A) of the DMG-SJIGBT has been diminished by 23% as a result of this structural modification. Gate engineering improves the transconductivity by increasing the gate-emitter capacitance (CGE) and reducing the gate-collector capacitance (CGC), which lowers switching delay. To improve performance metrics, the gate length has been optimized. A mixed mode module of SILVACO has used to perform capacitance-voltage analysis. Further the gate charge and FOM has also been measured and indicating 36% and 34% respectively reduction for proposed device signifying enhanced performance.
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