Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation

In this paper, we propose a feasible architecture with high precision and low resource consumption to compute the $N$th root of a floating-point number, which is mainly based on radix-4 SRT and 2-based Coordinate Rotation Digital Computer (CORDIC). Simulation results show that our method can achieve a relative error of the magnitude of 10−7. Under the same precision requirements, the hardware implementation results show a better performance of our design in terms of area, power, and absolute delay compared with the method based on the generalized hyperbolic CORDIC. After synthesizing it under the TSMC $40n$ m CMOS technology, it can be obtained that our design can achieve an area consumption of $125465.80\ \mu m^{2}$ and power consumption of 97.8062 mW at the highest frequency of 3.12 GHz.