A Novel Implementation of Ternary Decoder Using CMOS DPL Binary Gates

This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates, in digital CMOS technology. The physical design of the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. The Proposed Ternary Decoder circuit can be used in VLSI design. The Proposed decoder circuit will be the basic circuit to create other Ternary Logic Circuits like Ternary Logic Gates, Ternary Memory, Adder, Multiplier, Multiplexer, and others. The simulation results demonstrate the merits of the approach in terms of reduced number of transistors by 25% compared to the existing ternary decoder.