40nm CMOS工艺中具有布局依赖效应的电感建模

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2012-03-01 DOI:10.1109/SIRF.2012.6160144

E. Lourandakis, K. Nikellis, S. Stefanou, S. Bantas

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引用次数: 3

摘要

布局依赖效应(LDE)，因为他们是在现代半导体技术过程中遇到的解决和考虑在这项工作。基于40纳米工艺制备和表征器件的实验结果，讨论了它们对电感建模的影响。提出的基于向量的建模方法考虑了这些影响，并通过与实验数据的比较证明了其有效性。通过考虑与布局相关的影响，证明了与电感量L和质量因子Q等测量电感指标的改善相关性。

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Inductor modeling with layout-dependent effects in 40nm CMOS process

Layout-dependent effects (LDE) as they are encountered in modern semiconductor technology processes are addressed and considered in this work. In particular, their effect on inductor modeling is discussed based on experimental results of devices fabricated and characterized in a 40 nm technology process. The proposed vector based modeling approach is accounting for these effects and its validity is demonstrated by comparison to experimental data. Improved correlation to measured inductor metrics such as inductance L and quality factor Q is demonstrated by considering the layout-dependent effects.

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2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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