C. Pacha, K. Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C. Cleavelin, K. Schruefer, J. Berthold
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Efficiency of low-power design techniques in multi-gate FET CMOS circuits
Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.
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