带n-缓冲区的200V超级结MOSFET的设计与沟槽填充制程

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI:10.1109/WCT.2004.239903

Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, H. Yamaguchi

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引用次数: 22

摘要

设计并演示了一种新型的超级结沟槽MOSFET，该沟槽栅极和n列之间有n个缓冲区。在这种结构中，只要在沟槽栅极底部覆盖n缓冲器，即使栅极位置从设计位置移动，也不会增加比导通电阻(R/sub ON/)。漂移区由结构中的p/n柱组成，采用沟槽填充外延法形成。制备的SJ-MOSFET具有4 /spl mu/m的细节间距，其RON为2.3 n/spl Omega/。在203v击穿电压(V/sub / BR/)下，cm/sup 2/R/sub /比硅的极限低35%。

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Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling

A new super junction trench MOSFET, which has n-buffer regions between trench gates and n columns, was designed and demonstrated. In this structure, the specific on-resistance (R/sub ON/) does not increase as long as the trench gate bottom is covered with the n buffer, even though the gate position shifts from the designed one. The drift region, consisting of p/n columns in the structure, were formed by a trench filling epitaxial method. The fabricated SJ-MOSFET with a fine cell pitch of 4 /spl mu/m showed an RON of 2.3 n/spl Omega/.cm/sup 2/ at a breakdown voltage (V/sub BR/) of 203 V. The R/sub on/ is 35% lower than that of the silicon limit.

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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

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