{"title":"450mhz 1.0 V至1.8 V双向混合电压I/O缓冲采用90纳米工艺","authors":"Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu","doi":"10.1109/ICICDT.2010.5510290","DOIUrl":null,"url":null,"abstract":"A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process\",\"authors\":\"Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu\",\"doi\":\"10.1109/ICICDT.2010.5510290\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.\",\"PeriodicalId\":187361,\"journal\":{\"name\":\"2010 IEEE International Conference on Integrated Circuit Design and Technology\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Conference on Integrated Circuit Design and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2010.5510290\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process
A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.
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