Adaptive reduction of the frequency search space for multi-vdd digital circuits

Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular V dd /f max behavior of the die under test. This paper aims at adaptively reducing the search space for f max at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.