优化并行逻辑仿真的机器学习方法

S. Meraji, C. Tropper
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引用次数: 6

摘要

并行离散事件仿真可以作为一种快速、经济的方法应用于当前VLSI电路的门级仿真。本文将动态负载均衡算法和有界窗口算法结合起来进行乐观门电平仿真。有限的时间窗口可以防止模拟过于乐观和过度回滚。我们利用机器学习算法(Qlearning)来实现这种组合。我们引入了两种动态负载平衡算法来平衡通信和计算负载,并使用两个学习代理来组合这些算法。一个学习代理将两种学习算法结合起来,学习它们对应的参数,而第二个学习代理优化时间窗口的值。实验结果表明,使用该组合算法对多个开源电路的仿真时间提高了46%。据我们所知,这是Q-learning第一次被用于优化乐观门级模拟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Machine Learning Approach for Optimizing Parallel Logic Simulation
Parallel discrete event simulation can be applied as a fast and cost effective approach for the gate level simulation of current VLSI circuits. In this paper we combine a dynamic load balancing algorithm and a bounded window algorithm for optimistic gate level simulation. The bounded time window prevents the simulation from being too optimistic and from excessive rollbacks. We utilize a machine learning algorithm (Qlearning) to effect this combination. We introduce two dynamic load-balancing algorithms for balancing the communication and computational load and use two learning agents to combine these algorithms. One learning agent combines the two learning algorithms and learns their corresponding parameters, while the second optimizes the value of the time window. Experimental results show up to a 46% improvement in the simulation time using this combined algorithm for several open source circuits. To the best of our knowledge, this is the first time that Q-learning has been used to optimize an optimistic gate level simulation.
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