设计并实现了VLSI阵列处理器的一种多层视觉系统架构

Proceedings The International Conference on Application Specific Array Processors Pub Date : 1995-07-24 DOI:10.1109/ASAP.1995.522913

B. Saha, J. S. Mertoguno, N. Bourbakis

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摘要

本文介绍了KYDON视觉系统底层处理器的VLSI设计与仿真。KYDON是一个完全自主的、分层的、多层的图像理解系统。给出了各部件的VLSI设计以及处理器阵列的时序仿真结果。该系统运行频率为50兆赫，并保证了300帧/秒的高处理速率。

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The VLSI design and implementation of the array processors of a multilayer vision system architecture

This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 image frames/sec.

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Proceedings The International Conference on Application Specific Array Processors

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