用于硬件编译的专用数据流架构

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track Pub Date : 1989-01-03 DOI:10.1109/HICSS.1989.47158

M. Naini

{"title":"用于硬件编译的专用数据流架构","authors":"M. Naini","doi":"10.1109/HICSS.1989.47158","DOIUrl":null,"url":null,"abstract":"A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A dedicated data flow architecture for hardware compilation\",\"authors\":\"M. Naini\",\"doi\":\"10.1109/HICSS.1989.47158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<<ETX>>\",\"PeriodicalId\":300182,\"journal\":{\"name\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HICSS.1989.47158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

描述了一种专用的数据流体系结构，它被设计为硬件编译器的一部分。该机器通过接受属性语法的反向依赖图(类似于数据流图)，以数据流的方式评估属性语法。这些评估的输出和结果被发送到其他组件供以后使用。这台机器被认为是第一个专门用于此目的的数据流架构。它在两个层面上利用了并行性:首先，机器的组件以流水线方式组织，可以并发运行;其次，指令的执行也是并行完成的

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A dedicated data flow architecture for hardware compilation

A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

自引率

0.00%

发文量