David A. Yokoyama-Martin, K. Krishna, J. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, J. Parker, Ross Segelken, J. Sonntag, K. Umino, J. Upton, D. Weinlader, Skye Wolfer
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A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS
A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMC's 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and receive blocks
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