正则和前馈时钟方案下电源噪声和抖动的频谱关系

O. Vikinski
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引用次数: 1

摘要

高频电源噪声影响芯片性能的机制超出了逻辑路径故障,由于电压下降。高频噪声导致芯片性能下降的主要机制之一是直接引入时钟抖动。傅立叶分析支持的基本建模研究有助于建立对噪声如何在时钟分布路径中转化为抖动的清晰而基本的理解。在这种情况下,振荡器的前馈机制也被探索,其频谱响应的分析揭示了如何,一旦调谐得当,它有利于频率提升。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Spectral relations of supply noise and jitter with regular and feed forward clocking schemes
High frequency supply noise affects chip performance in mechanisms that go beyond logic path failures due to voltage drops. One of the dominant chip performance degradation mechanisms due to high frequency noise is the direct introduction of clock jitter. Basic modeling studies powered by Fourier analysis help establish a clear and fundamental understanding of how noise is translated into jitter in the clock distribution path. In this context oscillator feed forward mechanism is also explored and analysis of its spectral response reveals how, once tuned properly, it benefits frequency boost.
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