电阻漂移对多电平PCM设计的影响

2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI:10.1109/ICICDT.2010.5510298

Yi-Hsuan Chiu, Yi-Bo Liao, M. Chiang, C. Lin, W. Hsu, P. Chiang, Y. Hsu, Wenhsing Liu, S. Sheu, K. Su, M. Kao, M. Tsai

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引用次数: 5

摘要

介绍了多电平相变存储器的设计问题和见解。基于一个基于测量数据校准的紧凑模型，我们评估了电阻漂移对多层电池设计的影响。由于设计窗口在高温下可能会退化和恶化，因此必须特别注意开发可行的多层设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of resistance drift on multilevel PCM design

Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.

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来源期刊

2010 IEEE International Conference on Integrated Circuit Design and Technology

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