Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor

FDSOI is one of the alternative device architectures chosen to extend CMOS scaling for high-k metal gate. FDSOI is ideal for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). One of the challenges in FDSOI integration is to obtain a low gate to source drain capacitance (overlap capacitance or DC capacitance). To enable this, low k spacer material is needed. In this study we compared two ALD low-k spacer materials namely SiOCN and SiBCN against the conventional SiN spacer. Material characterization reveals SiOCN has lower etch rate than SiBCN. Both materials have good thermal stability. Transistors with SiOCN and SiBCN spacers were formed. Implementation of low-k spacer does not have significant impact on VT variability and oxygen ingress. Transistors with SiOCN and SiBCN spacer exhibited lower DC and AC capacitance without transistor resistance degradation.