Reliability Improvement of Static Random Access Memory Bit-Cells

The rapid growth in the semiconductor industry has paved the pathway for tremendous advancement in semiconductor memory technology. Internet of Things (IoT), wireless body sensor nodes and other high-end applications need power-efficient and reliable memories. Static Random Access Memory which is the heart of the chip occupies the major part of the area due to its importance. The demand for low power, deeply integrated and high-speed memory results in trade off between stability and area of the bit-cell, which are the two essential aspects of memory. As technology shrinks, the reliability of the memory gets affected. The stability involves soft error upset due to radiation in the working environment and the static noise margin is reduced due to process variation and operating conditions. In this paper, the SRAM bit-cell, which have both recovery from soft error upset and stability improvement by various read/write assist techniques, are discussed. The memory cells are designed using Cadence Virtuoso tool GPDK 180nm technology.