T. Matsuyama, N. Asada, M. Aoyama, A. Kamashita, H. Asazu, H. Yamamoto, K. Ogawa
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引用次数: 0
摘要
本文简要介绍了基于递归环面架构(T. Matsuyama et al.， 1993)设计的并行机RTA/1 (1024 pe)的硬件设计。我们开发了一个小型的原型机，有16个pe, RTA/0，以评估其性能。然后，我们提出了一种基于RTA/1的数据级并行处理方案，并通过在RTA/0上实现复杂的自底向上对象识别并行处理来验证其实用性。
Data level parallel processing for object recognition on Recursive Torus Architecture
The paper gives a brief overview of the hardware design of RTA/1 (with 1024 PEs), a parallel machine designed based on the Recursive Torus Architecture (T. Matsuyama et al., 1993). We developed a small scale prototype machine with 16 PEs, RTA/0, to evaluate its performance. Then, we propose a scheme of data level parallel processing on RTA/1 and demonstrate its utilities by implementing complex parallel processes for bottom up object recognition on RTA/0.
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