An Ultrahigh Speed AES Processor Method Based on FPGA

The realization of an ultrahigh speed AES processor based on FPGA is proposed in this paper, which can generate secure information at a constant rate of dozens of Gbps. Having compared with some other researches in terms of structure of the processor, speed and latency, we develop ultrahigh speed architectures for a reformulated version of AES algorithm, which shows a greater superiority than other ones currently. The merit comes that: Firstly, the processor is able to process 128 bits data during each clock period, only bringing 10 clock periods latency and saving 4K storage space. Secondly, we used a same and symmetric pipelining structure but different connection order and stored different initial keys in inner register when designing decryption module. Thus, the processor seems to be an asymmetrical system. Thirdly, the method that data involved in multiplication in Galois field was stored in ROM is used as the key to guarantee the safety of data and prohibit tampering.