Multilevel Converter Topologies with Internally Paralleled Power Stages

This paper discusses the synthesis of high-level multilevel converter topologies. Existing topologies are reviewed first, and it shows that these topologies are classified as three types based on their synthesis principles. The pros and cons of each type are discussed and summarized. Then a new topology synthesis concept, i.e. the Internal Parallelization (IP), is introduced. Experimental results using two examples are provided to verify their functionalities. Finally, design considerations of a 70kW high density inverter with 1500V DC link capability are presented.