{"title":"多米诺双轨，高速，NOR逻辑，采用90nm CMOS技术，300mV电源","authors":"A. Dadashi, O. Mirmotahari, Y. Berg","doi":"10.1109/ISCE.2016.7797398","DOIUrl":null,"url":null,"abstract":"A new ultra low voltage (ULV) dual- rail NOR gate is presented in this paper, which uses the semi-floating-gate (SFG) technique to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations, are the main advantage of the proposed gate in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.","PeriodicalId":193736,"journal":{"name":"2016 IEEE International Symposium on Consumer Electronics (ISCE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Domino dual-rail, high-speed, NOR logic, with 300mV supply in 90 nm CMOS technology\",\"authors\":\"A. Dadashi, O. Mirmotahari, Y. Berg\",\"doi\":\"10.1109/ISCE.2016.7797398\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new ultra low voltage (ULV) dual- rail NOR gate is presented in this paper, which uses the semi-floating-gate (SFG) technique to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations, are the main advantage of the proposed gate in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.\",\"PeriodicalId\":193736,\"journal\":{\"name\":\"2016 IEEE International Symposium on Consumer Electronics (ISCE)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Consumer Electronics (ISCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCE.2016.7797398\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Consumer Electronics (ISCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.2016.7797398","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Domino dual-rail, high-speed, NOR logic, with 300mV supply in 90 nm CMOS technology
A new ultra low voltage (ULV) dual- rail NOR gate is presented in this paper, which uses the semi-floating-gate (SFG) technique to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations, are the main advantage of the proposed gate in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
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