BPSK调解调系统在Spartan-3E FPGA上的仿真与实现

2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) Pub Date : 2019-11-01 DOI:10.1109/ICSSIT46314.2019.8987788

A.K. Thasleem Sulthana

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引用次数: 0

摘要

本文的目标是在Spartan 3E FPGA上重新制定和执行BPSK框架。在发射机组中完成的平衡标志，忽略一个信道并作为解调器发送到第二个单元。调节信号在解调器端完成。BPSK框架被用作CDMA创新的一部分。该框架利用VHDL方言进行模拟，并在两个Spartan 3E Starter单元表上实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Simulation and Implementation of BPSK Modulator and Demodulator System on Spartan-3E FPGA

The target of this paper is to re-enact and execute the BPSK framework on Spartan 3E FPGA. The balanced flag accomplished in transmitter pack, disregarded a channel and transmitted to second unit acts as demodulator. The adjusting signal accomplished at end of demodulator. BPSK framework is utilized as a part of is generally utilized as a part of CDMA innovation. This framework is mimicked by utilizing VHDL dialect and actualized on two Spartan 3E Starter unit sheets.

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2019 International Conference on Smart Systems and Inventive Technology (ICSSIT)

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