D. Aimé, C. Fenouillet-Béranger, P. Perreau, S. Denorme, J. Coignus, A. Cros, D. Fleury, O. Faynot, A. Vandooren, R. Gassilloud, F. Martin, S. Barnola, T. Salvetat, G. Chabanne, L. Brevard, M. Aminpur, F. Leverd, R. Gwoziecki, F. Boeuf, C. Hobbs, A. Zauner, M. Muller, V. Cosnier, S. Minoref, D. Bensahel, M. Orlowski, H. Mingam, A. Wild, S. Deleonibus, T. Skotnicki
{"title":"采用WXN金属栅极和HfSixOyNZ高k电介质的全耗尽SOI CMOS技术","authors":"D. Aimé, C. Fenouillet-Béranger, P. Perreau, S. Denorme, J. Coignus, A. Cros, D. Fleury, O. Faynot, A. Vandooren, R. Gassilloud, F. Martin, S. Barnola, T. Salvetat, G. Chabanne, L. Brevard, M. Aminpur, F. Leverd, R. Gwoziecki, F. Boeuf, C. Hobbs, A. Zauner, M. Muller, V. Cosnier, S. Minoref, D. Bensahel, M. Orlowski, H. Mingam, A. Wild, S. Deleonibus, T. Skotnicki","doi":"10.1109/ESSDERC.2007.4430926","DOIUrl":null,"url":null,"abstract":"This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric\",\"authors\":\"D. Aimé, C. Fenouillet-Béranger, P. Perreau, S. Denorme, J. Coignus, A. Cros, D. Fleury, O. Faynot, A. Vandooren, R. Gassilloud, F. Martin, S. Barnola, T. Salvetat, G. Chabanne, L. Brevard, M. Aminpur, F. Leverd, R. Gwoziecki, F. Boeuf, C. Hobbs, A. Zauner, M. Muller, V. Cosnier, S. Minoref, D. Bensahel, M. Orlowski, H. Mingam, A. Wild, S. Deleonibus, T. Skotnicki\",\"doi\":\"10.1109/ESSDERC.2007.4430926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文描述了一种全耗尽SOI技术的制造和电气性能，该技术使用直接金属栅极和高k介电集成在300 mm SOI晶圆上，用于低功耗应用。我们报道了在HfSiON栅极电介质上具有WN金属栅极(覆有TiN)的超薄FDSOI MOS晶体管。演示了器件和电路级的性能，并与TiN中隙金属栅极进行了比较。
Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric
This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
