15.8 A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs

Active gate control is an emerging technique to minimize the switching loss of high-power converters facing noise-suppression challenges. In a conventional gate-driver design, a fixed value of gate resistance is chosen by the converter designers so that the slew rate (SR) of the drain voltage Vd, namely $dV_{d}/$dt, does not exceed noise-aware design guidelines in each application and use case. Minimizing the gate resistance leads to high $dV_{d}/$dt and the reduction in switching loss while shortening the turn-on delay for the overall converter performance. However, the impact is limited because of uncontrollable $dV_{d}/$dt drift caused by load-current, temperature, and $\mathrm {V}_{th}$ variations of the power transistors. Thus, in practice there is significant room for further loss and turn-on-delay minimization for the active gate control that adaptively modulates gate driving ability within every switching cycle.