30.3 A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems

High-bandwidth (BW) and large-capacity storage systems with NAND Flash memory (hereinafter referred to as “NAND”) have been increasingly required for big data applications, such as the field of advanced biomedical science [1]. However, a conventional NAND interface (I/F), e.g., Toggle DDR, with multi-drop bus topology has a tradeoff between BW and capacity due to the large load capacitance of NAND packages (PKGs). Although increasing the number of parallelized lanes of Toggle DDR improves both BW and capacity, it costs a large number of pins/wires on a controller/PCB. In order to overcome these problems, a daisy-chained serial I/F has been proposed [2]. In the I/F, bridge chips mask large load capacitance of NAND PKGs seen from a controller’s transmitter (TX) so that a 12.8Gb/s downlink is realized. However, the multi-band multiplexing technique employed in [2] has a drawback in the difficulty in implementing an uplink because severe timing control is required for cumulatively multiplexing multiple bands (i.e., channels) in each bridge chip. In order to realize both a downlink and an uplink with lower power consumption, this paper presents a newly developed serial I/F with three key techniques: (1) PAM-4-based 4-channel (4-ch) multiplexing, (2) cascaded CDR circuits in (3) ring topology. The fabricated transceiver (TRX) for the proposed I/F achieves 3.69pJ/b with a BER lower than 10-15 at 25.Gb/s with PRBS31 through 1.84dB of channel loss at 6.4GHz. The proposed I/F can achieve a state-of-the-art FoM (defined as “# of packages × Data Rate / power consumption”) of 1.80PKG.Gb/s/mW.