Hossein Doroud, M. Ghorbanian, R. Sabbaghi‐Nadooshan
{"title":"方形拓扑:noc的一种新颖拓扑","authors":"Hossein Doroud, M. Ghorbanian, R. Sabbaghi‐Nadooshan","doi":"10.1109/NORCHP.2011.6126731","DOIUrl":null,"url":null,"abstract":"This paper proposes square topology as an efficient topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. In our simulation, the proposed square topology had better performance in comparison to other topologies specifically meshes and spidergon topology.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Square topology: A novel topology for NoCs\",\"authors\":\"Hossein Doroud, M. Ghorbanian, R. Sabbaghi‐Nadooshan\",\"doi\":\"10.1109/NORCHP.2011.6126731\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes square topology as an efficient topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. In our simulation, the proposed square topology had better performance in comparison to other topologies specifically meshes and spidergon topology.\",\"PeriodicalId\":108291,\"journal\":{\"name\":\"2011 NORCHIP\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 NORCHIP\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2011.6126731\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2011.6126731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper proposes square topology as an efficient topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. In our simulation, the proposed square topology had better performance in comparison to other topologies specifically meshes and spidergon topology.