verilog HDL的程序差分算法

A. Duley, Christopher J. Spandikow, Miryung Kim
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引用次数: 25

摘要

在代码审查任务期间,使用现有的程序差异工具(如diff)比较硬件设计描述的两个版本本质上是有限的,因为现有的程序差异工具隐式地假设顺序执行语义,而硬件描述语言被设计为建模并发计算。我们设计了一个位置无关的差分算法来鲁棒地处理相对顺序无关的语言结构。本文给出了该位置无关差分算法在Verilog HDL中的一个实例Vdiff。为了帮助程序员在高层次上理解差异,Vdiff根据verilog特定的更改类型输出语法差异。我们在两个开源硬件设计项目中评估了Vdiff。评估结果表明,Vdiff是非常准确的,当使用人工分类的差异作为比较基础时,总体精度为96.8%,召回率为97.3%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A program differencing algorithm for verilog HDL
During code review tasks, comparing two versions of a hardware design description using existing program differencing tools such as diff is inherently limited because existing program differencing tools implicitly assume sequential execution semantics, while hardware description languages are designed to model concurrent computation. We designed a position-independent differencing algorithm to robustly handle language constructs whose relative orderings do not matter. This paper presents Vdiff, an instantiation of this position-independent differencing algorithm for Verilog HDL. To help programmers reason about the differences at a high-level, Vdiff outputs syntactic differences in terms of Verilog-specific change types. We evaluated Vdiff on two open source hardware design projects. The evaluation result shows that Vdiff is very accurate, with overall 96.8% precision and 97.3% recall when using manually classified differences as a basis of comparison.
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