横向非均匀掺杂和热载流子退化对高压 MOSFET 电容行为的影响

Y. Chauhan, R. Gillon, M. Declercq, A. Ionescu
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引用次数: 9

摘要

本文采用器件仿真的方法对LDMOS、VDMOS等高压MOSFET (HV-MOS)的电容特性进行了详细分析。分别分析了横向不均匀掺杂和漂移区的影响。结果表明,HV-MOS的CGD和CGS电容峰是由横向不均匀掺杂引起的。漂移区降低了CGD电容,增加了CGS的峰值,并且随着漏极偏置的增加,CGG电容的峰值也增加了。由于热载流子降解引起的捕获电荷根据漏极或源侧的热孔或电子注入调节(或引入)电容中的峰值振幅和位置。这种电容分析将有助于优化HV-MOS结构,也有助于HV-MOS的建模,包括热载子降解。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impact of lateral non-uniform doping and hot carrier degradation on capacitance behavior of high voltage MOSFETs
In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in CGD and CGS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the CGD capacitance and increases the peaks in CGS and also gives rise to peaks in CGG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.
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