A high performance motion vector processor IP design for H.264/AVC

In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 times 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 times 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.