J-machine多计算机:体系结构评价

Proceedings of the 20th Annual International Symposium on Computer Architecture Pub Date : 1993-05-01 DOI:10.1145/165123.165158

M. Noakes, D. Wallach, W. Dally

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引用次数: 303

摘要

构建了MIT J-Machine多计算机，以研究一组基本机制在为并行计算提供有效支持方面的作用。每个J-Machine节点由一个集成的多计算机组件、消息驱动处理器(Message-Driven Processor, MDP)和1mbyte的DRAM组成。MDP提供了支持高效通信、同步和命名的机制。一个512节点的J-Machine正在运作，并将在1993年3月扩大到1024节点。在本文中，我们讨论了J-Machine的设计，并评估了纳入MDP的机制的有效性。我们直接测量了通信和同步机制的性能，并研究了四个完整应用程序的行为。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The J-machine Multicomputer: An Architectural Evaluation

The MIT J-Machine multicomputer has been constructed to study the role of a set of primitive mechanisms in providing efficient support for parallel computing. Each J-Machine node consists of an integrated multicomputer component, the Message-Driven Processor (MDP), and 1 MByte of DRAM. The MDP provides mechanisms to support efficient communication, synchronization, and naming. A 512 node J-Machine is operational and is due to be expanded to 1024 nodes in March 1993. In this paper we discuss the design of the J-Machine and evaluate the effectiveness of the mechanisms incorporated into the MDP. We measure the performance of the communication and synchronization mechanisms directly and investigate the behavior of four complete applications.

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Proceedings of the 20th Annual International Symposium on Computer Architecture

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