Thread Progress Aware Block Migration for Dynamic NUCA

Non-Uniform Cache Architecture (NUCA) is a viable solution for large capacity on-chip caches to manage the increasing wire delay. Dynamic NUCA divides the last-level cache (LLC) into smaller cache banks connected by on-chip network. D-NUCA yields good performance through migrating blocks within bank sets at runtime to harness data locality. Various works have well explored and studied D-NUCA, including block migration, mapping and searching. However, all of the previous D-NUCA design are thread-oblivious. Due to the interference on shared resources, threads often demonstrate unbalanced progress wherein the lagging threads with slow progress are more critical to overall performance. In this paper, we propose a novel D-NUCA design called Thread prOgress aware block Migration (TOM). TOM exploits the dynamic thread criticality information to control block migration. TOM aims at boosting the execution of critical threads through biased block migration. Experimental results show that TOM can effectively reduce the execution time of a set of PARSEC applications with less energy dissipation compared with previous D-NUCA design.