{"title":"基于模型的多处理器总线仲裁器设计与分布式实现","authors":"Imene Ben Hafaiedh, S. Graf, Mohamad Jaber","doi":"10.1109/ICECS.2011.6122215","DOIUrl":null,"url":null,"abstract":"The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Model-based design and distributed implementation of bus arbiter for multiprocessors\",\"authors\":\"Imene Ben Hafaiedh, S. Graf, Mohamad Jaber\",\"doi\":\"10.1109/ICECS.2011.6122215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Model-based design and distributed implementation of bus arbiter for multiprocessors
The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.
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