1T1C feram自适应参考生成方案

T. Chandler, A. Sheikholeslami, S. Masui, M. Oura
{"title":"1T1C feram自适应参考生成方案","authors":"T. Chandler, A. Sheikholeslami, S. Masui, M. Oura","doi":"10.1109/VLSIC.2003.1221193","DOIUrl":null,"url":null,"abstract":"A reference time, instead of a reference voltage, is generated used to compare stored \"0\" and \"1\" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An adaptive reference generation scheme for 1T1C FeRAMs\",\"authors\":\"T. Chandler, A. Sheikholeslami, S. Masui, M. Oura\",\"doi\":\"10.1109/VLSIC.2003.1221193\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A reference time, instead of a reference voltage, is generated used to compare stored \\\"0\\\" and \\\"1\\\" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221193\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221193","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

生成一个参考时间,而不是一个参考电压,用于比较存储的“0”和“1”在一组位线中达到1T1C FeRAM的阈值电压。参考时间是自适应的,跟踪铁电电容器的工艺变化、老化和疲劳。该方案在一个256/spl次/128位测试芯片上以0.35 /spl mu/m的铁电工艺实现,在3v电压下实现了40ns的访问时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An adaptive reference generation scheme for 1T1C FeRAMs
A reference time, instead of a reference voltage, is generated used to compare stored "0" and "1" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.
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