{"title":"一种5 ghz SiGe HBT归零比较器","authors":"Weinan Gao, W. Snelgrove, S. Kovacic","doi":"10.1109/BIPOL.1995.493890","DOIUrl":null,"url":null,"abstract":"A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"39","resultStr":"{\"title\":\"A 5-GHz SiGe HBT return-to-zero comparator\",\"authors\":\"Weinan Gao, W. Snelgrove, S. Kovacic\",\"doi\":\"10.1109/BIPOL.1995.493890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.\",\"PeriodicalId\":230944,\"journal\":{\"name\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"39\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1995.493890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1995.493890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A monolithic comparator implemented in a SiGe HBT technology is presented. The circuit employs a resettable slave stage, which was carefully designed to produce return-to-zero output data. Operation with sampling rates up to 5-GHz has been demonstrated. The comparator chip has an input range of 1.5 V, dissipates 89 mW from a 3-volt supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/.
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