Simulation of marked graphs on SIMD architectures using efficient memory management

This paper describes and evaluates the performance of an implementation of a parallel discrete event simulation of a class of Petri nets known as marked graphs on a single instruction stream multiple data stream (SIMD) architecture. The implementation uses an efficient, novel memory management technique for supporting abstract data types, where memory can be dynamically allocated/deallocated on an individual PE basis. Performance evaluations are reported for a number of "real world" applications.<>