使用忆阻器的倍增器设计

2017 IEEE International Conference on IC Design and Technology (ICICDT) Pub Date : 2017-05-23 DOI:10.1109/ICICDT.2017.7993521

Lauren Guckert, E. Swartzlander

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引用次数: 2

摘要

由于其独特的存储能力和高密度，记忆电阻器最近成为未来系统设计的领导者。这项工作提出了一个优化的dada倍增器使用忆阻器和暗示逻辑。该设计将基准延迟降低了30%，复杂性降低了50%，并且元件数量少于CMOS设计的60%。该设计也是流水线化的，达到CMOS的3倍吞吐量。

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Dadda Multiplier designs using memristors

Memristors have recently become a leader in future system design due to their unique storage abilities and high density. This work presents an optimized Dadda Multiplier using memristors and IMPLY logic. The design reduces the baseline delay by 30% and complexity by 50% and has fewer than 60% the components of the CMOS design. The design is also pipelined to achieve 3× the throughput of CMOS.

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2017 IEEE International Conference on IC Design and Technology (ICICDT)

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