可靠性增强技术中的边信道效应研究

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI:10.1109/DFT.2009.32

Jianwei Dai, Lei Wang

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引用次数: 12

摘要

可靠性增强技术对于在各种物理非理想性(如工艺变化和制造缺陷)压力下的纳米级集成系统至关重要。然而，目前尚不清楚这些技术将如何影响通过硬件实现泄露的侧信道信息。相关的侧信道效应可能直接影响到广泛应用中的安全需求。本文对可信硬件设计中的这一新问题进行了研究。采用信息论的方法，定量评价了可靠性增强与诱导侧信道效应之间的关系。最后给出了存储电路中EDC/ECC方案的仿真结果，以验证所提方法的应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Study of Side-Channel Effects in Reliability-Enhancing Techniques

Reliability-enhancing techniques are critical for nanoscale integrated systems under the pressure of various physical non-idealities such as process variations and manufacturing defects. However, it is unclear how these techniques will affect the side-channel information leaked through hardware implementations. The related side-channel effects may have direct implications to the security requirement in a wide range of applications. In this paper, we investigate this new problem for trusted hardware design. Employing information-theoretic measures, the relationship between reliability enhancements and the induced side-channel effects is quantitatively evaluated. Simulation results on EDC/ECC schemes in memory circuits are presented to demonstrate the application of the proposed method.

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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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