D. Durackova, Mário Krajmer, J. Racko, J. Breza, M. Kadlecíková
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Some simulated properties of the pseudostructure of a floating gate MOS transistor
The floating gate technology is widely used as a memory element in digital circuits and as a novel memory element in analogue technology. In this work we prepare the basis for on-chip implementation of a Cellular Neural Network (CNN). For this purpose we investigate the features of a pseudo-floating gate transistor introduced in [1]. After simulating the structure by T-CAD tool we designed a behavioural model in SPICE that could be implemented into CADENCE design tool.
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