大型集成电路版图检查系统

Papers on Twenty-five years of electronic design automation Pub Date : 1988-06-01 DOI:10.1145/62882.62899

Kenji Yoshida, T. Mitsuhashi, Y. Nakada, Toshiaki Chiba, Kiyoshi Ogita, S. Nakatsuka

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引用次数: 10

摘要

本文介绍了一种新型的LSI掩模图案规则检测系统。该系统的主要特点是所需的计算时间相对较小，即使对于非常大的电路(例如10,000个元件)，由于其功能灵活性，广泛应用于各种制造工艺，并且最大限度地减少了杂散误差。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A layout checking system for large scale integrated circuits

This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.

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Papers on Twenty-five years of electronic design automation

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