90纳米高密度ASIC芯片后端工艺优化

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) Pub Date : 2003-06-02 DOI:10.1109/IITC.2003.1219731

P. Zarkesh-Ha, P. Wright, S. Lakshminarayanan, C. Cheng, W. Loh, W. Lynch

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引用次数: 7

摘要

根据ASIC产品的市场、方法和制造要求，提出了90nm高密度ASIC芯片的最佳后端工艺。高密度ASIC芯片的芯片尺寸大致保持在7到14毫米之间。高密度芯片实现与紧密的间距为所有路由水平。较薄的金属2和3 Cu厚度为0.25，而较高的金属厚度为0.35 /spl mu/m时，性能最佳。

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Backend process optimization for 90 nm high-density ASIC chips

Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 /spl mu/m for the higher levels of metal.

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来源期刊

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

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