Prospective graphene-based through silicon vias in three-dimensional integrated circuits

The package of the silicon chip is an important aspect of VLSI. The package determines the size of ICs. Different IC packages allow the dies to connect with the PCB and it affects the performance of IC. These packages offer a connection with PCB, atmosphere protection and mechanical stability for the IC. The demand of improvement in IC package is increasing day by day due to the increased density of IC. The design of packages grew from through-hole to surface mount technology, from WB to flip -chip and from dual-inline packaging to chip scale packaging. Although there has been tremendous progress in this area, it is in the middle of another evolution. This progress is the evaluation of the 3D packaging design. This design provides more than 100% PE and enhances performance metrics through decreased interconnection length. This is achieved by vertical connections of stacking chips using TSVs. Vertically connected TSVs also facilitate heterogeneous integration of dies in realising on a single chip. However, the selection of filler material in TSVs plays a vital role in the reliability of 3D ICs. There are some challenges in the areas of thermal management and electrical design. In the present study, four different surrounding materials, that is, SiO2 , Si3N4 , Al203 and Hf0 2 have been considered. The equivalent stress and the resultant structure deformation of filler material (Cu and CNT) of TSVs are observed. It is noticed that the deformation in the structure of CNT-based TSVs is lesser as compared to Cu -based TSVs. Further, Hf0 2 possesses significantly lesser deformation as compared to SiO2 and Al2O3.