VHDL的一个行为子集的指称语义

Proceedings Design, Automation and Test in Europe Pub Date : 1998-02-23 DOI:10.1109/DATE.1998.655996

F. Nicoli

{"title":"VHDL的一个行为子集的指称语义","authors":"F. Nicoli","doi":"10.1109/DATE.1998.655996","DOIUrl":null,"url":null,"abstract":"This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Denotational semantics of a behavioral subset of VHDL\",\"authors\":\"F. Nicoli\",\"doi\":\"10.1109/DATE.1998.655996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.\",\"PeriodicalId\":179207,\"journal\":{\"name\":\"Proceedings Design, Automation and Test in Europe\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-02-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Design, Automation and Test in Europe\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DATE.1998.655996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Design, Automation and Test in Europe","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.1998.655996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了VHDL的一个行为子集的指称语义。这个子集仅限于基本数据类型，不允许在等待语句中使用子句。充分考虑了模型的时间和分辨率，给出了仿真机制的精确定义。从该语义可以推导出从VHDL到Boyer-Moore逻辑的简单转换规则。

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Denotational semantics of a behavioral subset of VHDL

This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.

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Proceedings Design, Automation and Test in Europe

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